This invention relates in general to data communications circuits, and in particular to an adaptive peak detector for data communications receivers.
In baseband digital communication systems, information is typically encoded in a series of pulses that are transmitted over the communication channel. The pulse stream of logical zeros and ones are detected at the receiver end to regenerate the information. For error free regeneration of the transmitted signal, the receiver must accurately detect the logic levels of the received signal. To establish the threshold voltage between a logical one and a logical zero, receivers typically first apply the incoming signal to a peak detect circuit. The peak detect circuit provides a DC reference corresponding to the peak value of the input signal. The peak value is then divided to produce threshold levels at, for example, 50% of the detected peak value. Comparators are then used to recover the pulses by slicing the input signal around the threshold levels.
Most peak detect circuits acquire the peak of an input signal by first rectifying it and then allowing the rectified signal to charge or discharge a capacitor. A typical example of a positive peak detect circuit is shown in FIG. 1. A comparator 100 receives the input signal Vin at its positive input. The negative input of comparator 100 connects to the output of the circuit Vpk, a capacitor 102 and the source terminal of an N-channel MOS transistor 104. The output of comparator 100 drives the gate terminal of transistor 104, whose drain connects to a supply voltage. In operation, assume that capacitor 102 is initially discharged such that Vpk and the negative input of comparator 100 are at ground. As the input signal Vin rises above ground, the output of comparator 100 goes high, turning on transistor 104. Transistor 104 acts as a source-follower and charges capacitor 102, thereby raising the output voltage Vpk. This voltage is fed back to the negative input of the comparator. Thus, as long as the input signal Vin continues to rise, capacitor 102 is charged through transistor 104. When the signal Vin reaches its peak value, transistor 104 stops charging capacitor 102, and Vpk is held at the peak value minus the threshold voltage for transistor 104. Capacitor 102 will be incrementally charged every time the signal at Vin rises above the preceding peak value. Thus, the circuit provides at the output Vpk, a DC voltage representing the peak value of the input signal Vin.
circuit speed and dynamic range are among the most important factors in the design of a peak detect circuit. The peak of the input signal must be acquired as early as possible so that the receiver can start detecting the signal. A very fast peak detector can detect the peak of the incoming signal after the reception of a few pulses. Typical system specifications require the acquisition of the peak within about 20 clock cycles. The speed of the circuit is primarily governed by the input signal amplitude and the charge current for a given peak detection capacitor size. That is, the peak detection capacitor must be charged faster to reach a larger peak value within the same time period. This is accomplished by adjusting the charge transistor size which in turn adjusts the charge current to the capacitor. Input signal amplitude also governs the dynamic range performance of the circuit. Typical CMOS or bipolar comparators have a fixed dynamic range. Their design centers the window of operation at either high input voltages or low input voltages. Signal distortion and output offset occurs if a signal outside the dynamic range of the comparator is applied to its inputs.
Because of the above considerations, the design of peak detect circuits is typically optimized for either small or large input signals. This, however, creates problems when there are large amplitude variations in the input signal. Variations in the length of the communication line cause variations in signal amplitude. As a result, peak values for the transmitted signal may vary significantly depending on the channel length. Another drawback of the above peak detect circuit is that due to temperature dependence of the charge current, the speed of the circuit varies with changes in temperature conditions. Also, because of the use of the source-follower, the peak detector output is always one threshold voltage below the actual peak of the input signal. The limited dynamic range and temperature dependence of the peak detect circuit give rise to large offsets and reduce the accuracy of peak detection. Peak detection offset results in non-optimum slicing levels for the comparators inside the receiver. This in turn increases the probability of bit errors.
There is therefore a need for an accurate peak detect circuit that enjoys a wide dynamic range for use in data communication systems.